The present invention relates to a semiconductor static memory device and, particularly, to an improvement of such semiconductor static memory device, whereby the power consumption of the device is minimized.
FIG. 1 shows a memory unit of a typical conventional semiconductor static memory device in which reference numerals 1, 2, 3, and 8a and 8b depict a memory cell, a word line, bit lines, and bit line loads, respectively. The memory cell 1 is composed of inverter transistors 4a and 4b, access transistors 5a and 5b, load resistors 6a and 6b, and memory nodes 7a and 7b. A plurality of such memory units are connected to the word line 2, and a plurality of the word lines 2 are arranged in parallel so that memory units arranged in the same vertical position constitute a column, thereby forming a matrix of the memory units. A row decoder is connected to each word line and a column decoder is provided for each column so that a particular memory unit can be accessed by activating the corresponding row decoder and column decoder.
In such a static memory device, information is stored at the memory nodes 7a and 7b. Assuming that the memory nodes 7a and 7b store an H (high-level information bit) and an L (low-level information bit), respectively, a current (referred to as a "column current") flows from a power source V.sub.cc through the bit line load 8b, the access transistor 5b, and the inverter transistor 4b of the memory cell 1 to a ground point when the memory cell 1 is selected by setting the word line 2 to the H level. However, a problem arises in such a static RAM in that the column current flows into all memory cells connected to a word line 2 activated by a row decoder. The column current flowing into memory cells in columns other than that selected by a column decoder results in a waste of power.
In order to reduce such ineffective column currents, as proposed in Japanese Kokai Publication No. 55-122290, of which one of the applicants is the present inventor, each word line can be divided into a pair of word line segments and a row decoder associated with the word line arranged between the word line segments. In this case, only one of the word line segments is activated at any one time, thereby reducing in half the column current.
In order to further reduce the ineffective column current, it has proposed, as disclosed in Japanese KoKai Publication No. 58-211393, whose equivalent is U.S. Pat. No. 4,542,486, of which one of the applicants is the present inventor, to divide each word line into a number of word line segments so that each segment belongs to a block of columns and to activate one of the word line segments by using a row selection line and a column block selection signal. The latter proposal is very effective and has been put to actual practice in a 64K static RAM. (See ISSCC Digest of Technical Papers, pp. 58, 59 (February 1983)). However, this system requires the addition of row selection lines parallel to the word lines, causing the structure of each memory cell to be complicated.
As another approach of reducing the column current, Japanese Kokai Publication No. 56-143587, whose equivalent is U.S. Pat. No. 4,409,679, proposes to increase the potential of ground terminals of memory cells in columns not selected. However, this approach is unsuccessful in completely eliminating unwanted column currents, and, since each ground line is commonly used by all of the memory cells in a column, the associated parasitic capacitance, which is a load on the ground line, is large, resulting in a large current required to charge and discharge it.
ISSCC Digest of Technical Papers, pp. 258, 259 (February 1982), and ISSCC Digest of Technical Papers, pp. 260, 261 (February 1982) disclose a method of driving a bit line load with a pulse to cut out the column current. This method is effective in reducing the steady-state component of the column current, but is ineffective in eliminating the transient component thereof.